The present invention relates, in general, to the field of integrated circuit memory devices and those devices incorporating embedded dynamic random access memory (DRAM). More particularly, the present invention relates to a sense amplifier power-gating technique of particular utility with respect to DRAM devices, or those incorporating embedded DRAM, having a power-down (or Sleep) mode of operation.
Many types of DRAM based devices, or integrated circuits including embedded memory arrays, are currently available including extended data out (“EDO”), synchronous DRAM (“SDRAM”), double data rate (“DDR”) DRAM and the like. Regardless of configuration, the primary purpose of the DRAM is to store data. Functionally, data may be written to the memory, read from it or periodically refreshed to maintain the integrity of the stored data. In current high density designs, each DRAM memory cell comprises a pass transistor coupled to an associated capacitor that may be charged to store a value representative of either a logic level “1” or “0”. Data stored in these memory cells may be read out and written to them through columns of sense amplifiers coupled to complementary bit lines interconnecting rows of these cells.
Certain sense amplifier designs have included cross-coupled complementary metal oxide semiconductor (“CMOS”) latches made up of cross coupled inverters comprising series connected P-channel and N-channel transistors. The common connection of the P-channel devices is generally referred to as the latch P-channel (“LP”) node while the corresponding common connection of the N-channel devices is denominated the latch N-channel (“LN”) node.
Among the possible layouts for columns of such sense amplifiers is to provide a common LP and LN driver device for all of the sense amplifiers. While such an approach may have certain advantages, the LP and LN driver transistors must be very large and the corresponding LP and LN signal lines must be relatively wide. Because of this, relatively slow latching speeds may be experienced resulting in concomitantly slow “read” and “write” speeds. Moreover, data patterns may be encountered which can cause failures such as a logic level “1” in a field of “0s” will tend to latch very late if the number of sense amplifiers in the column is large.
In an attempt to ameliorate certain of these disadvantages, other sense amplifier layouts have incorporated the use of distributed LP and LN drivers in which a relatively smaller pull-up and pull-down transistor is included in each sense amplifier cell instead of much larger devices common to an entire column of sense amplifiers. Through the use of this technique, narrower LPB (latch P-channel bar) and LNB (latch N-channel bar) signal lines may be run to each sense amplifier cell in a column.
Power-gating has also been used in logic circuits to reduce Sleep Mode power. This is achieved by adding transistors in the VCC and VSS supply paths of the distributed LP (pull-up) and LN (pull-down) driver transistors associated with each sense amplifier cell. These power gate transistors are turned “on” during an Active Mode and turned “off” during Sleep Mode to reduce the total static current due to transistor “off” current. Typically, the gate terminals of the power gate transistors are forced to higher than VCC (in the case of P-channel devices) or lower than VSS (in the case of N-channel devices) voltage levels so that their voltage gate-to-source (VGS) is negative. This reduces the “off” current of these transistors significantly.
However, since there would typically be a large number of sense amplifiers coupled to these power gate transistors, and all of these sense amplifiers would be switching at about the same time, the current surge through the power gate transistors during a sensing operation ends up being very large. This current surge causes a voltage drop across the power gate transistors which tends to have the same effect as reducing the level of VCC, thereby degrading sensing speed. Furthermore, these sense amplifier power gate transistors must, of necessity, be made extremely large to avoid degrading circuit speed too much, (although such degradation nonetheless occurs to at least some extent) thereby consuming a great deal of on-chip area.